As a scaling technique for enhancing the density of a semiconductor device, a multi-gate transistor has been proposed in which a fin-like silicon body is formed on a substrate and a gate is formed on a surface of a silicon body.
Since such a multi-gate transistor utilizes three-dimensional channels, it may be easily scaled. Further, the current control capability can be improved even without increasing the gate length of the multi-gate transistor. Furthermore, it is possible to effectively suppress SCE (short channel effect) in which the potential of the channel region is affected by the drain voltage.